Home > Articles

  • Print
  • + Share This
This chapter is from the book

Rambus Memory (RDRAM)

All the memory systems that we've talked about so far are known as wide channel systems because the memory channel is equal to the width of the processor bus. RDRAM is known as a narrow channel system because data is transferred only 2 bytes (16 bits) at a time. This might seem small, but those 2 bytes move extremely fast! The Rambus data bus is 16 bits wide, as opposed to the more typical 32 or 64 bits wide. Additionally, Rambus memory sends data more frequently. It reads data on both the rising and falling edges of the clock signal.


Rambus dynamic RAM comes out of technology developed originally by Rambus, Inc., for the Nintendo 64 gaming system. It's not that new, but it seems new because Intel started to use it with its Pentium 4 processors and 800-series chipset. Rambus memory is integrated onto Rambus Inline Memory Modules (RIMMs). The modules use Rambus DRAM (RDRAM) chips. We discuss memory modules (packaging) later in this chapter.

RDRAM chips use the processor's memory bus timing frequency, not the motherboard clock. Therefore, the processor won't request something at mid tick (the reverse of an interrupt). On the other hand, SRAM and SDRAM are synced to the CPU at a multiple closer to the motherboard clock. In other words, SDRAM, running at 100MHz, might be three times the speed of a 33MHz board.

RDRAM starts with the CPU speed, multiplied from a 66MHz board. A 10X processor on the same board would now be running at 660MHz. RDRAM then sets the memory bus to one half or one third of the CPU speed. 660 divided by two sets the memory bus at 330MHz. Divide by three, and the memory bus transfers at 220MHz. Both are faster than SDRAM. Remember that speed alone doesn't account for total performance.

Earlier Pentiums used a 64-bit bus and transferred data in parallel. The corresponding memory module bus was also 64 bits wide, which meant that data could be moved across the memory bus in 64-bit (8-byte) chunks. Another way of looking at it is that a bit is one-eighth of a byte. Therefore, 64 bits divided by 8 equals 8 bytes.


Earlier memory chips used separate address, data, and control lines. This separation tended to limit speed. Engineers decided that joining the three types of data into a single packet and moving it across a single bus would improve efficiency. Along the way, they came up with two different methods, or protocols, for doing so. The protocol-based designs we'll mention are SyncLink DRAM (SLDRAM) and Rambus DRAM, sometimes called Direct Rambus DRAM (DRDRAM).

Intel eventually bought Rambus and began licensing the technology for a fee. SLDRAM, on the other hand, was an open industry standard. You may remember the problems IBM had with their micro-channel architecture buses. In the same way, memory manufacturers moved more toward SLDRAM. A secondary benefit of SLDRAM was that it doesn't require that existing RAM chips be redesigned. RDRAM, with its narrow channel bus, is a whole new architecture.

The original SLDRAM used a 200Mhz bus, making it faster than standard SDRAM. Double Data Rate SDRAM (DDR SDRAM) and SLDRAM both use the rising and falling edge of the clock to move twice the amount of information as SDRAM. As such, the overall transfer started out at 400MHz and quickly moved up to 800MHz.

Prior to Rambus memory, the fastest chips had a throughput of 100MHz. SDRAM with a 64-bit bus (to match the Pentium) transfers data in 8-byte chunks. Eight megabytes moving in parallel means an 8MB transfer every second. RDRAM chips transfer data in 2-byte chunks, twice per cycle (one on the up tick, one on the down tick). At 800MHz, RIMMs move 1,600MB per second (2 transfers per cycle times 800), which translates to 1.66 gigabytes (GB) or a billion bytes—about twice as fast as SDRAM.

  • + Share This
  • 🔖 Save To Your Account